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core-3399jd4的arm linux系统,停在bootconsole [uart0] disabled处

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技术小白

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发表于 2020-10-29 13:57:27     
使用核心板core-3399jd4,配合MB-JD4-RK3399 V1.1 主板。
编译官方提供的firefly-sdk-20200629.7z的arm linux系统,编译成功烧录到核心板上,系统启动后,停止在bootconsole [uart0] disabled处,不再向下运行。

具体开机信息日志如下,有知道的群友或官方技术人员帮忙解决下,多谢!

`\0\0\0\0DDR Version 1.24 20191016
In
channel 0
CS = 0
MR0=0x98
MR4=0x3
MR5=0xFF
MR8=0x8
MR12=0x72
MR14=0x72
MR18=0x0
MR19=0x0
MR24=0x8
MR25=0xFF
channel 1
CS = 0
MR0=0x98
MR4=0x3
MR5=0xFF
MR8=0x8
MR12=0x72
MR14=0x72
MR18=0x0
MR19=0x0
MR24=0x8
MR25=0xFF
channel 0 training pass!
channel 1 training pass!
change freq to 416MHz 0,1
Channel 0: LPDDR4,416MHz
Bus Width=32 Col=10 Bank=8 Row=15 CS=1 Die Bus-Width=16 Size=1024MB
Channel 1: LPDDR4,416MHz
Bus Width=32 Col=10 Bank=8 Row=15 CS=1 Die Bus-Width=16 Size=1024MB
256B stride
channel 0
CS = 0
MR0=0x98
MR4=0x3
MR5=0xFF
MR8=0x8
MR12=0x72
MR14=0x72
MR18=0x0
MR19=0x0
MR24=0x8
MR25=0xFF
channel 1
CS = 0
MR0=0x98
MR4=0x3
MR5=0xFF
MR8=0x8
MR12=0x72
MR14=0x72
MR18=0x0
MR19=0x0
MR24=0x8
MR25=0xFF
channel 0 training pass!
channel 1 training pass!
channel 0, cs 0, advanced training done
channel 1, cs 0, advanced training done
change freq to 856MHz 1,0
ch 0 ddrconfig = 0x101, ddrsize = 0x20
ch 1 ddrconfig = 0x101, ddrsize = 0x20
pmugrf_os_reg[2] = 0x3281F281, stride = 0x9
ddr_set_rate to 328MHZ
ddr_set_rate to 666MHZ
ddr_set_rate to 416MHZ, ctl_index 0
ddr_set_rate to 856MHZ, ctl_index 1
support 416 856 328 666 MHz, current 856MHz
OUT
Boot1 Release Time: Dec 24 2019 18:00:26, version: 1.24
CPUId = 0x0
ChipType = 0x10, 338
SdmmcInit=2 0
BootCapSize=100000
UserCapSize=14910MB
FwPartOffset=2000 , 100000
mmc0:cmd8,20
mmc0:cmd5,20
mmc0:cmd55,20
mmc0:cmd1,20
mmc0:cmd8,20
mmc0:cmd5,20
mmc0:cmd55,20
mmc0:cmd1,20
mmc0:cmd8,20
mmc0:cmd5,20
mmc0:cmd55,20
mmc0:cmd1,20
SdmmcInit=0 1
StorageInit ok = 68362
SecureMode = 0
SecureInit read PBA: 0x4
SecureInit read PBA: 0x404
SecureInit read PBA: 0x804
SecureInit read PBA: 0xc04
SecureInit read PBA: 0x1004
SecureInit read PBA: 0x1404
SecureInit read PBA: 0x1804
SecureInit read PBA: 0x1c04
SecureInit ret = 0, SecureMode = 0
atags_set_bootdev: ret:(0)
GPT part:  0, name:            uboot, start:0x4000, size:0x2000
GPT part:  1, name:            trust, start:0x6000, size:0x2000
GPT part:  2, name:             misc, start:0x8000, size:0x2000
GPT part:  3, name:             boot, start:0xa000, size:0x10000
GPT part:  4, name:         recovery, start:0x1a000, size:0x10000
GPT part:  5, name:           backup, start:0x2a000, size:0x10000
GPT part:  6, name:              oem, start:0x3a000, size:0x20000
GPT part:  7, name:           rootfs, start:0x5a000, size:0xc00000
GPT part:  8, name:         userdata, start:0xc5a000, size:0x10c4fdf
find part:uboot OK. first_lba:0x4000.
find part:trust OK. first_lba:0x6000.
LoadTrust Addr:0x6000
No find bl30.bin
Load uboot, ReadLba = 4000
Load OK, addr=0x200000, size=0xda214
RunBL31 0x40000 @ 109722 us
NOTICE:  BL31: v1.3(release):57824cc
NOTICE:  BL31: Built : 10:59:12, Jan  6 2020
NOTICE:  BL31: Rockchip release version: v1.1
INFO:    GICv3 with legacy support detected. ARM GICV3 driver initialized in EL3
INFO:    Using opteed sec cpu_context!
INFO:    boot cpu mask: 0
INFO:    plat_rockchip_pmu_init(1190): pd status 3e
INFO:    BL31: Initializing runtime services
INFO:    BL31: Initializing BL32
INF [0x0] TEE-CORE:init_primary_helper:337: Initializing (1.1.0-230-g6c76e8a9 #191 Mon Nov 18 07:00:24 UTC 2019 aarch64)

INF [0x0] TEE-CORE:init_primary_helper:338: Release version: 1.2

INF [0x0] TEE-CORE:init_teecore:83: teecore inits done
INFO:    BL31: Preparing for EL3 exit to normal world
INFO:    Entry point address = 0x200000
INFO:    SPSR = 0x3c9


U-Boot 2017.09 (Oct 29 2020 - 11:18:22 +0800)

Model: Firefly-RK3399 Board
PreSerial: 2
DRAM:  2 GiB
Sysmem: init
Relocation Offset is: 7dbeb000
Using default environment

dwmmc@fe320000: 1, sdhci@fe330000: 0
Bootdev(atags): mmc 0
MMC0: HS400, 150Mhz
PartType: EFI
boot mode: None
Load FDT from boot part
DTB: rk-kernel.dtb
I2c speed: 400000Hz
PMIC:  RK808
vdd_center 900000 uV
vdd_cpu_l 900000 uV
vdd_log 1100000 uV
In:    serial
Out:   serial
Err:   serial
Model: AIO-3399-JD4 Board (Linux Opensource)
Rockchip UBOOT DRM driver version: v1.0.1
CLK: (uboot. arml: enter 816000 KHz, init 816000 KHz, kernel 0N/A)
CLK: (uboot. armb: enter 24000 KHz, init 24000 KHz, kernel 0N/A)
  aplll 816000 KHz
  apllb 24000 KHz
  dpll 856000 KHz
  cpll 24000 KHz
  gpll 800000 KHz
  npll 600000 KHz
  vpll 24000 KHz
  aclk_perihp 133333 KHz
  hclk_perihp 66666 KHz
  pclk_perihp 33333 KHz
  aclk_perilp0 266666 KHz
  hclk_perilp0 88888 KHz
  pclk_perilp0 44444 KHz
  hclk_perilp1 100000 KHz
  pclk_perilp1 50000 KHz
Net:   eth0: ethernet@fe300000
Hit key to stop autoboot('CTRL+C'):  2  1  0
ANDROID: reboot reason: "(none)"
Fdt Ramdisk skip relocation
Booting IMAGE kernel at 0x00280000 with fdt at 0x8300000...


## Booting Android Image at 0x0027f800 ...
Kernel load addr 0x00280000 size 22211 KiB
RAM disk load addr 0x0a200000 size 8675 KiB
## Flattened Device Tree blob at 08300000
   Booting using the fdt blob at 0x8300000
   XIP Kernel Image ... OK
  'reserved-memory' region@110000: addr=110000 size=f0000
   Using Device Tree in place at 0000000008300000, end 000000000831c68a
Adding bank: 0x00200000 - 0x08400000 (size: 0x08200000)
Adding bank: 0x0a200000 - 0x80000000 (size: 0x75e00000)
Can't find file:logo_kernel.bmp
Total: 2753.578 ms

Starting kernel ...

[    0.000000] Booting Linux on physical CPU 0x0
[    0.000000] Initializing cgroup subsys cpuset
[    0.000000] Initializing cgroup subsys cpu
[    0.000000] Initializing cgroup subsys cpuacct
[    0.000000] Linux version 4.4.194 (wangyuan@zoncare-R730) ((no: 7ec0922c96d1e6298bb0e4499117625bffe304fe update) (gcc version 6.3.1 20170404 (Linaro GCC 6.3-2017.05) ) #2 SMP Thu Oct 29 11:24:54 CST 2020
[    0.000000] Boot CPU: AArch64 Processor [410fd034]
[    0.000000] earlycon: Early serial console at MMIO32 0xff1a0000 (options '')
[    0.000000] bootconsole [uart0] enabled
[    0.000000] psci: probing for conduit method from DT.
[    0.000000] psci: PSCIv1.0 detected in firmware.
[    0.000000] psci: Using standard PSCI v0.2 function IDs
[    0.000000] psci: Trusted OS migration not required
[    0.000000] PERCPU: Embedded 21 pages/cpu @ffffffc07fedf000 s46312 r8192 d31512 u86016
[    0.000000] Detected VIPT I-cache on CPU0
[    0.000000] CPU features: enabling workaround for ARM erratum 845719
[    0.000000] Built 1 zonelists in Zone order, mobility grouping on.  Total pages: 507912
[    0.000000] Kernel command line: storagemedia=emmc androidboot.storagemedia=emmc androidboot.mode=normal  androidboot.slot_suffix= androidboot.serialno=42a965000a1ca93e  ro rootwait earlycon=uart8250,mmio32,0xff1a0000 swiotlb=1 root=PARTLABEL=rootfs rootfstype=ext4 overlayroot=device:dev=PARTLABEL=userdata,fstype=ext4,mkfs=1 coherent_pool=1m systemd.gpt_auto=0 cgroup_enable=memory swapaccount=1
[    0.000000] PID hash table entries: 4096 (order: 3, 32768 bytes)
[    0.000000] Dentry cache hash table entries: 262144 (order: 9, 2097152 bytes)
[    0.000000] Inode-cache hash table entries: 131072 (order: 8, 1048576 bytes)
[    0.000000] software IO TLB: mapped [mem 0x7fe97000-0x7fed7000] (0MB)
[    0.000000] Memory: 1993412K/2064384K available (13886K kernel code, 1794K rwdata, 5284K rodata, 1216K init, 2007K bss, 70972K reserved, 0K cma-reserved)
[    0.000000] Virtual kernel memory layout:
[    0.000000]     modules : 0xffffff8000000000 - 0xffffff8008000000   (   128 MB)
[    0.000000]     vmalloc : 0xffffff8008000000 - 0xffffffbdbfff0000   (   246 GB)
[    0.000000]       .init : 0xffffff8009340000 - 0xffffff8009470000   (  1216 KB)
[    0.000000]       .text : 0xffffff8008080000 - 0xffffff8008e10000   ( 13888 KB)
[    0.000000]     .rodata : 0xffffff8008e10000 - 0xffffff8009340000   (  5312 KB)
[    0.000000]       .data : 0xffffff8009470000 - 0xffffff8009630808   (  1795 KB)
[    0.000000]     vmemmap : 0xffffffbdc0000000 - 0xffffffbfc0000000   (     8 GB maximum)
[    0.000000]               0xffffffbdc0008000 - 0xffffffbdc2000000   (    31 MB actual)
[    0.000000]     fixed   : 0xffffffbffe7fb000 - 0xffffffbffec00000   (  4116 KB)
[    0.000000]     PCI I/O : 0xffffffbffee00000 - 0xffffffbfffe00000   (    16 MB)
[    0.000000]     memory  : 0xffffffc000200000 - 0xffffffc080000000   (  2046 MB)
[    0.000000] SLUB: HWalign=64, Order=0-3, MinObjects=0, CPUs=6, Nodes=1
[    0.000000] Hierarchical RCU implementation.
[    0.000000]         Build-time adjustment of leaf fanout to 64.
[    0.000000]         RCU restricting CPUs from NR_CPUS=8 to nr_cpu_ids=6.
[    0.000000] RCU: Adjusting geometry for rcu_fanout_leaf=64, nr_cpu_ids=6
[    0.000000] NR_IRQS:64 nr_irqs:64 0
[    0.000000] GIC: Using split EOI/Deactivate mode
[    0.000000] ITS: /interrupt-controller@fee00000/interrupt-controller@fee20000
[    0.000000] ITS: allocated 65536 Devices @7d480000 (psz 64K, shr 0)
[    0.000000] ITS: using cache flushing for cmd queue
[    0.000000] GIC: using LPI property table @0x000000007d410000
[    0.000000] ITS: Allocated 1792 chunks for LPIs
[    0.000000] CPU0: found redistributor 0 region 0:0x00000000fef00000
[    0.000000] CPU0: using LPI pending table @0x000000007d420000
[    0.000000] GIC: using cache flushing for LPI property table
[    0.000000] GIC: PPI partition interrupt-partition-0[0] { /cpus/cpu@0[0] /cpus/cpu@1[1] /cpus/cpu@2[2] /cpus/cpu@3[3] }
[    0.000000] GIC: PPI partition interrupt-partition-1[1] { /cpus/cpu@100[4] /cpus/cpu@101[5] }
[    0.000000] rockchip_clk_register_frac_branch: could not find dclk_vop0_frac as parent of dclk_vop0, rate changes may not work
[    0.000000] rockchip_clk_register_frac_branch: could not find dclk_vop1_frac as parent of dclk_vop1, rate changes may not work
[    0.000000] rockchip_cpuclk_pre_rate_change: limiting alt-divider 33 to 31
[    0.000000] Architected cp15 timer(s) running at 24.00MHz (phys).
[    0.000000] clocksource: arch_sys_counter: mask: 0xffffffffffffff max_cycles: 0x588fe9dc0, max_idle_ns: 440795202592 ns
[    0.000006] sched_clock: 56 bits at 24MHz, resolution 41ns, wraps every 4398046511097ns
[    0.002277] Console: colour dummy device 80x25
[    0.002707] console [tty0] enabled
[    0.003043] bootconsole [uart0] disabled
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技术小白

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发表于 2020-12-30 17:45:45     
这种情况一般是 device .mk文件选择不对造成的,需要选择与开发板对应的 board .mk文件,通常不会出现异常问题。
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