Core-3399-JD4官方标配的LVDS屏 timing参数疑问
disp_timings: display-timings {native-mode = <&timing0>;
timing0: timing0 {
clock-frequency = <166000000>; //166000000 @50
hactive = <800>;
vactive = <1280>;
hsync-len = <10>; //20, 50
hback-porch = <100>; //50, 56
hfront-porch = <1580>;//50, 30 //1580
vsync-len = <10>;
vback-porch = <25>;
vfront-porch = <10>;
hsync-active = <0>;
vsync-active = <0>;
de-active = <0>;
pixelclk-active = <0>;
};
这是Core-3399-JD4官网DTS文件
为什么clock-frequency = <166000000>; //166000000 @50为什么不是等于DCLK65000000？？
hfront-porch = <1580>;//50, 30 //1580为什么会取这么大呢？？
我参考官方标配的LVDS屏手册DCLK Frequency t CLK 60 65 70 MHz
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