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标题: RK3328 android 版本串口无法使用，无 ttyS1 设备节点！！！ [打印本页]

作者: dapeng 时间: 2018-3-4 14:31
标题: RK3328 android 版本串口无法使用，无 ttyS1 设备节点！！！

最近一个项目要使用 rk3328 接串口外设，发现官网的 wifi 有问题，ttySx 节点都没有。

http://www.t-firefly.com/doc/product/info/id/263.html

4) 接收数据

首先在设备上运行下列命令：

cat /dev/ttyS1复制代码

然后在主机的串口终端输入字符串 “Firefly uart1 test...”，设备端即可见到相同的字符串。

ttyS1设备节点都没有，操作个毛线，也不知道如何打开，请问你们rk3328的 git 代码能不能更新一下，懂 Kernel 应该配置一下，很简单的吧，这么简单的事情都做不好么。

作者: dapeng 时间: 2018-3-4 14:32
自己尝试改了下 dts，还是没有 ttyS1

diff --git a/arch/arm64/boot/dts/rk3328-roc-cc-port.dtsi b/arch/arm64/boot/dts/rk3328-roc-cc-port.dtsi
index a66214d..10c4af1 100644
--- a/arch/arm64/boot/dts/rk3328-roc-cc-port.dtsi
+++ b/arch/arm64/boot/dts/rk3328-roc-cc-port.dtsi
@@ -53,6 +53,60 @@
            status = "okay";
      };

+       aliases {
+             serial0 = &uart0;
+             serial1 = &uart1;
+             serial2 = &uart_dbg;
+       };
+
+       uart0: serial@ff110000 {
+             compatible = "rockchip,serial";
+             reg = <0x0 0xff110000 0x0 0x100>;
+             interrupts = <GIC_SPI 55 IRQ_TYPE_LEVEL_HIGH>;
+             clock-frequency = <24000000>;
+             clocks = <&clk_uart0>, <&clk_gates16 11>;
+             clock-names = "sclk_uart", "pclk_uart";
+             reg-shift = <2>;
+             reg-io-width = <4>;
+             dmas = <&pdma 2>, <&pdma 3>;
+             #dma-cells = <2>;
+             pinctrl-names = "default";
+             pinctrl-0 = <&uart0_xfer &uart0_cts &uart0_rts>;
+             status = "disabled";
+       };
+
+       uart1: serial@ff120000 {
+             compatible = "rockchip,serial";
+             reg = <0x0 0xff120000 0x0 0x100>;
+             interrupts = <GIC_SPI 56 IRQ_TYPE_LEVEL_HIGH>;
+             clock-frequency = <24000000>;
+             clocks = <&clk_uart1>, <&clk_gates16 12>;
+             clock-names = "sclk_uart", "pclk_uart";
+             reg-shift = <2>;
+             reg-io-width = <4>;
+             dmas = <&pdma 4>, <&pdma 5>;
+             #dma-cells = <2>;
+             pinctrl-names = "default";
+             pinctrl-0 = <&uart1_xfer &uart1_cts &uart1_rts>;
+             status = "okey";
+       };
+
+       uart_dbg: serial@ff130000 {
+             compatible = "rockchip,serial";
+             reg = <0x0 0xff130000 0x0 0x100>;
+             interrupts = <GIC_SPI 57 IRQ_TYPE_LEVEL_HIGH>;
+             clock-frequency = <24000000>;
+             clocks = <&clk_uart2>, <&clk_gates16 13>;
+             clock-names = "sclk_uart", "pclk_uart";
+             reg-shift = <2>;
+             reg-io-width = <4>;
+             dmas = <&pdma 6>, <&pdma 7>;
+             #dma-cells = <2>;
+             pinctrl-names = "default";
+             pinctrl-0 = <&uart2m1_xfer>;
+             status = "disabled";
+       };
+
      io-domains {
            status = "okay";

@@ -378,11 +432,20 @@
};

&uart0 {
-       status = "disabled";
-       dma-names = "!tx", "!rx";
-       pinctrl-0 = <&uart0_xfer &uart0_cts>;
+    status = "disabled";
+    dma-names = "!tx", "!rx";
+    pinctrl-0 = <&uart0_xfer &uart0_cts>;
+};
+
+&uart1{
+       status = "okey";
};

+&uart_dbg{
+       status = "okey";
+};
+

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