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【Linux】
rk3568 linux6.6 启动pcie3x1卡死
发表于 2024-7-25 13:22:56
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系统:openEuler based on linux 6.6
内核日志：
[ 0.614903] rockchip-dw-pcie 3c0000000.pcie: host bridge /pcie@fe260000 ranges:
[ 0.614970] rockchip-dw-pcie 3c0000000.pcie: IO 0x00f4100000..0x00f41fffff -> 0x00f4100000
[ 0.615052] rockchip-dw-pcie 3c0000000.pcie: MEM 0x00f4200000..0x00f5ffffff -> 0x00f4200000
[ 0.615096] rockchip-dw-pcie 3c0000000.pcie: MEM 0x0300000000..0x033fffffff -> 0x0040000000
[ 0.615350] rockchip-dw-pcie 3c0000000.pcie: iATU: unroll T, 8 ob, 8 ib, align 64K, limit 8G
[ 0.699803] mmc1: new HS200 MMC card at address 0001
[ 0.700655] mmcblk1: mmc1:0001 eMMC 7.20 GiB
[ 0.705671] mmcblk1: p1 p2 p3
[ 0.706792] mmcblk1boot0: mmc1:0001 eMMC 4.00 MiB
[ 0.708153] mmcblk1boot1: mmc1:0001 eMMC 4.00 MiB
[ 0.709471] mmcblk1rpmb: mmc1:0001 eMMC 4.00 MiB, chardev (238:0)
[ 1.721940] rockchip-dw-pcie 3c0000000.pcie: Phy link never came up
[ 1.722447] rockchip-dw-pcie 3c0000000.pcie: PCI host bridge to bus 0000:00
[ 1.722482] pci_bus 0000:00: root bus resource [bus 00-0f]
[ 1.722509] pci_bus 0000:00: root bus resource [io 0x0000-0xfffff] (bus address [0xf4100000-0xf41fffff])
[ 1.722531] pci_bus 0000:00: root bus resource [mem 0xf4200000-0xf5ffffff]
[ 1.722554] pci_bus 0000:00: root bus resource [mem 0x300000000-0x33fffffff] (bus address [0x40000000-0x7fffffff])
[ 1.722618] pci 0000:00:00.0: [1d87:3566] type 01 class 0x060400
[ 1.722666] pci 0000:00:00.0: reg 0x38: [mem 0x00000000-0x0000ffff pref]
[ 1.722766] pci 0000:00:00.0: supports D1 D2
[ 1.722784] pci 0000:00:00.0: PME# supported from D0 D1 D3hot
[ 1.728284] pci_bus 0000:01: busn_res: can not insert [bus 01-ff] under [bus 00-0f] (conflicts with (null) [bus 00-0f])
[ 1.728540] pci 0000:00:00.0: BAR 6: assigned [mem 0xf4200000-0xf420ffff pref]
[ 1.728575] pci 0000:00:00.0: PCI bridge to [bus 01-ff]
[ 1.731243] pcieport 0000:00:00.0: PME: Signaling with IRQ 49
[ 1.938653] phy phy-fe8c0000.phy.7: lane number 0, val 1
[ 1.938830] rockchip-dw-pcie 3c0400000.pcie: host bridge /pcie@fe270000 ranges:
[ 1.938892] rockchip-dw-pcie 3c0400000.pcie: IO 0x00f2100000..0x00f21fffff -> 0x00f2100000
[ 1.938932] rockchip-dw-pcie 3c0400000.pcie: MEM 0x00f2200000..0x00f3ffffff -> 0x00f2200000
[ 1.938964] rockchip-dw-pcie 3c0400000.pcie: MEM 0x0340000000..0x037fffffff -> 0x0040000000
[ 375.711588] rcu: INFO: rcu_sched detected stalls on CPUs/tasks:
[ 375.711635] rcu: 3-...0: (4 ticks this GP) idle=1934/1/0x4000000000000000 softirq=43/44 fqs=3601
[ 375.711663] rcu: (detected by 2, t=18006 jiffies, g=-1095, q=13 ncpus=4)
[ 375.711680] Task dump for CPU 3:
[ 375.711691] task:kworker/u8:2 state:R running task stack:0 pid:40 ppid:2 flags:0x0000000a
[ 375.711723] Workqueue: events_unbound deferred_probe_work_func
[ 375.711754] Call trace:
[ 375.711765] __switch_to+0x14c/0x170
[ 375.711788] 0xd83a799ad0336800
设备树dtsi相关：
pcie30_phy_grf: syscon@fdcb8000 {
compatible = "rockchip,rk3568-pcie3-phy-grf", "syscon";
reg = <0x0 0xfdcb8000 0x0 0x10000>;
};
pcie30phy: phy@fe8c0000 {
compatible = "rockchip,rk3568-pcie3-phy";
reg = <0x0 0xfe8c0000 0x0 0x20000>;
#phy-cells = <0>;
clocks = <&pmucru CLK_PCIE30PHY_REF_M>, <&pmucru CLK_PCIE30PHY_REF_N>,
<&cru PCLK_PCIE30PHY>;
clock-names = "refclk_m", "refclk_n", "pclk";
resets = <&cru SRST_PCIE30PHY>;
reset-names = "phy";
rockchip,phy-grf = <&pcie30_phy_grf>;
status = "disabled";
};
pcie3x1: pcie@fe270000 {
compatible = "rockchip,rk3568-pcie";
#address-cells = <3>;
#size-cells = <2>;
bus-range = <0x0 0xf>;
clocks = <&cru ACLK_PCIE30X1_MST>, <&cru ACLK_PCIE30X1_SLV>,
<&cru ACLK_PCIE30X1_DBI>, <&cru PCLK_PCIE30X1>,
<&cru CLK_PCIE30X1_AUX_NDFT>;
clock-names = "aclk_mst", "aclk_slv",
"aclk_dbi", "pclk", "aux";
device_type = "pci";
interrupts = <GIC_SPI 160 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 159 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 158 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 157 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 156 IRQ_TYPE_LEVEL_HIGH>;
interrupt-names = "sys", "pmc", "msg", "legacy", "err";
#interrupt-cells = <1>;
interrupt-map-mask = <0 0 0 7>;
interrupt-map = <0 0 0 1 &pcie3x1_intc 0>,
<0 0 0 2 &pcie3x1_intc 1>,
<0 0 0 3 &pcie3x1_intc 2>,
<0 0 0 4 &pcie3x1_intc 3>;
linux,pci-domain = <1>;
num-ib-windows = <6>;
num-ob-windows = <2>;
max-link-speed = <3>;
msi-map = <0x0 &gic 0x1000 0x1000>;
num-lanes = <1>;
phys = <&pcie30phy>;
phy-names = "pcie-phy";
power-domains = <&power RK3568_PD_PIPE>;
reg = <0x3 0xc0400000 0x0 0x00400000>,
<0x0 0xfe270000 0x0 0x00010000>,
<0x0 0xf2000000 0x0 0x00100000>;
ranges = <0x01000000 0x0 0xf2100000 0x0 0xf2100000 0x0 0x00100000>,
<0x02000000 0x0 0xf2200000 0x0 0xf2200000 0x0 0x01e00000>,
<0x03000000 0x0 0x40000000 0x3 0x40000000 0x0 0x40000000>;
reg-names = "dbi", "apb", "config";
resets = <&cru SRST_PCIE30X1_POWERUP>;
reset-names = "pipe";
/* bifurcation; lane1 when using 1+1 */
status = "disabled";
pcie3x1_intc: legacy-interrupt-controller {
interrupt-controller;
#address-cells = <0>;
#interrupt-cells = <1>;
interrupt-parent = <&gic>;
interrupts = <GIC_SPI 157 IRQ_TYPE_EDGE_RISING>;
};
};
pcie3x2: pcie@fe280000 {
compatible = "rockchip,rk3568-pcie";
#address-cells = <3>;
#size-cells = <2>;
bus-range = <0x0 0xf>;
clocks = <&cru ACLK_PCIE30X2_MST>, <&cru ACLK_PCIE30X2_SLV>,
<&cru ACLK_PCIE30X2_DBI>, <&cru PCLK_PCIE30X2>,
<&cru CLK_PCIE30X2_AUX_NDFT>;
clock-names = "aclk_mst", "aclk_slv",
"aclk_dbi", "pclk", "aux";
device_type = "pci";
interrupts = <GIC_SPI 165 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 164 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 163 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 162 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 161 IRQ_TYPE_LEVEL_HIGH>;
interrupt-names = "sys", "pmc", "msg", "legacy", "err";
#interrupt-cells = <1>;
interrupt-map-mask = <0 0 0 7>;
interrupt-map = <0 0 0 1 &pcie3x2_intc 0>,
<0 0 0 2 &pcie3x2_intc 1>,
<0 0 0 3 &pcie3x2_intc 2>,
<0 0 0 4 &pcie3x2_intc 3>;
linux,pci-domain = <2>;
num-ib-windows = <6>;
num-ob-windows = <2>;
max-link-speed = <3>;
msi-map = <0x0 &gic 0x2000 0x1000>;
num-lanes = <2>;
phys = <&pcie30phy>;
phy-names = "pcie-phy";
power-domains = <&power RK3568_PD_PIPE>;
reg = <0x3 0xc0800000 0x0 0x00400000>,
<0x0 0xfe280000 0x0 0x00010000>,
<0x0 0xf0000000 0x0 0x00100000>;
ranges = <0x01000000 0x0 0xf0100000 0x0 0xf0100000 0x0 0x00100000>,
<0x02000000 0x0 0xf0200000 0x0 0xf0200000 0x0 0x01e00000>,
<0x03000000 0x0 0x40000000 0x3 0x80000000 0x0 0x40000000>;
reg-names = "dbi", "apb", "config";
resets = <&cru SRST_PCIE30X2_POWERUP>;
reset-names = "pipe";
/* bifurcation; lane0 when using 1+1 */
status = "disabled";
pcie3x2_intc: legacy-interrupt-controller {
interrupt-controller;
#address-cells = <0>;
#interrupt-cells = <1>;
interrupt-parent = <&gic>;
interrupts = <GIC_SPI 162 IRQ_TYPE_EDGE_RISING>;
};
};
设备树dts相关：
vcc3v3_m2_pcie: vcc3v3-m2-pcie-regulator {
compatible = "regulator-fixed";
regulator-name = "m2_pcie_3v3";
// enable-active-high;
regulator-always-on;
regulator-boot-on;
regulator-min-microvolt = <3300000>;
regulator-max-microvolt = <3300000>;
// gpios = <&gpio0 RK_PD4 GPIO_ACTIVE_HIGH>;
// pinctrl-0 = <&vcc3v3_m2_pcie_en>;
pinctrl-names = "default";
startup-delay-us = <5000>;
vin-supply = <&vcc5v0_sys>;
};
&pcie30phy {
status = "okay";
};
&pcie3x2 {
rockchip,bifurcation;
reset-gpios = <&gpio2 RK_PD4 GPIO_ACTIVE_HIGH>;
vpcie3v3-supply = <&vcc3v3_m2_pcie>;
status = "okay";
pcie@20 {
reg = <0x00200000 0 0 0 0>;
#address-cells = <3>;
#size-cells = <2>;
rtl8125_2: pcie-eth@20,0 {
compatible = "pci10ec,8125";
reg = <0x000000 0 0 0 0>;
realtek,led-ledsel2 = <0x022b>;
realtek,led-ledsel3 = <0x002b>;
};
};
};
&pcie3x1 {
rockchip,bifurcation;
reset-gpios = <&gpio2 RK_PD5 GPIO_ACTIVE_HIGH>;
vpcie3v3-supply = <&vcc3v3_m2_pcie>;
status = "okay";
/*
pcie@10 {
reg = <0x00100000 0 0 0 0>;
#address-cells = <3>;
#size-cells = <2>;
rtl8125_1: pcie-eth@10,0 {
compatible = "pci10ec,8125";
reg = <0x000000 0 0 0 0>;
realtek,led-ledsel2 = <0x022b>;
realtek,led-ledsel3 = <0x002b>;
};
};*/
};
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