DDR Version V1.08 20210825
LPDDR4, 328MHz
BW=32 Col=10 Bk=8 CS0 Row=16 CS=1 Die BW=16 Size=2048MB
change to: 328MHz
change to: 528MHz
change to: 784MHz
change to: 924MHz(final freq)
out
U-Boot SPL board init
U-Boot SPL 2017.09(u-boot commit id: 617c0aeae793895dfbcfad2e0d67ce0620736a93)(sdk version: rv1126_rv1109_linux_release_20221222_v2.2.5d.xml)-g617c0aeae7 #lvsx (Dec 22 2022 - 10:32:10)
unknown raw ID phN
unrecognized JEDEC id bytes: 00, 00, 00
Trying to boot from MMC2
MMC: no card present
mmc_init: -123, time 2
spl: mmc init failed with error: -123
Trying to boot from MMC1
SPL: A/B-slot: _a, successful: 0, tries-remain: 7
## Verified-boot: 0
## Checking optee 0x08400000 (gzip @0x08600000) ... sha256(501681e1e7...) + sha256(447872e443...) + OK
## Checking uboot 0x00400000 (gzip @0x00600000) ... sha256(525d1d9d7f...) + sha256(7d3b5f9915...) + OK
## Checking fdt 0x004b6b14 ... sha256(80f00e7967...) + OK
Jumping to U-Boot(0x00400000) via OP-TEE(0x08400000)
Total: 119.99 ms
I/TC:
I/TC: cpu feature:0x0
I/TC: RV1126 SoC
I/TC: cpu_st=0xe0
I/TC: Next entry point address: 0x00400000
I/TC: OP-TEE version: 3.13.0-549-gef7f159d #derrick.huang (gcc version 6.3.1 20170404 (Linaro GCC 6.3-2017.05)) #1 Thu Oct 28 10:52:10 CST 2021 arm
I/TC: Primary CPU initializing
I/TC: Primary CPU switching to normal world boot