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发表于 2020-9-22 17:57:26
只看该作者
板凳
串口信息U-Boot 2017.09 (Jun 12 2019 - 11:15:10 +0800)
Model: Rockchip RK3399 Evaluation Board
DRAM: 3.8 GiB
Relocation Offset is: f5be0000
Using default environment
dwmmc@fe320000: 1, sdhci@fe330000: 0
Card did not respond to voltage select!
mmc_init: -95, time 9
switch to partitions #0, OK
mmc0(part 0) is current device
Bootdev: mmc 0
PartType: RKPARM
Load FDT from resource part
DTB: rk-kernel.dtb
I2c speed: 400000Hz
rk8xx_read: read reg 0xed failed, ret=-121
rk8xx_read: read reg 0xed failed, ret=-121
"Synchronous Abort" handler, esr 0x96000004
* Relocate offset = 00000000f5be0000
* ELR(PC) = 00000000002897f4
* LR = 000000000028a694
* SP = 00000000e9dd39d0
* ESR_EL2 = 0000000096000004
EC[31:26] == 100101, Exception from a Data abort, from current exception level
IL[25] == 1, 32-bit instruction trapped
* DAIF = 00000000000003c0
D[9] == 1, DBG masked
A[8] == 1, ABORT masked
I[7] == 1, IRQ masked
F[6] == 1, FIQ masked
* SPSR_EL2 = 0000000020000349
D[9] == 1, DBG masked
A[8] == 1, ABORT masked
I[7] == 0, IRQ not masked
F[6] == 1, FIQ masked
M[4] == 0, Exception taken from AArch64
M[3:0] == 1001, EL2h
* SCTLR_EL2 = 0000000030c51835
I[12] == 1, Icaches enabled
C[2] == 1, Dcache enabled
M[0] == 1, MMU enabled
* HCR_EL2 = 000000000800003a
* VBAR_EL2 = 00000000f5de0800
* TTBR0_EL2 = 00000000f7ff0000
x0 : 000001f84b415352 x1 : 000001f84b415351
x2 : 000001f84b415352 x3 : 00000000ffffffff
x4 : 00000000ffffffff x5 : 0000000000000000
x6 : 00000000ffffffd8 x7 : 00000000f5ea43f8
x8 : 00000000e9dd4120 x9 : 0000000000000008
x10: 00000000ffffffe0 x11: 0000000000000006
x12: 000000000001869f x13: 00000000f5ea7458
x14: 0000000000000000 x15: 00000000fffffffe
x16: 0000000000000001 x17: 0000000000000007
x18: 00000000e9dd7da0 x19: 000001f84b415352
x20: 00000000ffffffff x21: 00000000e9dd3d9a
x22: 00000000e9dd419c x23: 0000000000000000
x24: 00000000e9dd3d88 x25: 0000000000000020
x26: 00000000f5e95db9 x27: 00000000ffffffff
x28: 00000000e9dd419c x29: 00000000e9dd3bb0
SP:
e9dd39d0: 00000000 00000000 00000000 00000000
e9dd39e0: 00000000 00000000 f5e971e4 00000000
e9dd39f0: 00000000 00000000 00000000 00000000
e9dd3a00: f5e9722b 00000000 f5e97251 00000000
e9dd3a10: f5e9729e 00000000 f5e972eb 00000000
e9dd3a20: f5e9732b 00000000 f5e9736b 00000000
e9dd3a30: f5e973a8 00000000 00000000 00000000
e9dd3a40: 00000000 00000000 f5e973e5 00000000
e9dd3a50: e9dd3bb0 00000000 f5de0a0c 00000000
e9dd3a60: 4b415352 000001f8 ffffffff 00000000
e9dd3a70: f7ff0000 00000000 0800003a 00000000
e9dd3a80: 30c51835 00000000 e9dd39d0 00000000
e9dd3a90: 20000349 00000000 f5de0800 00000000
e9dd3aa0: 000003c0 00000000 96000004 00000000
e9dd3ab0: f5e697f4 00000000 4b415352 000001f8
e9dd3ac0: 4b415351 000001f8 4b415352 000001f8
Resetting CPU ...
DDR Version 1.15 20181010
In
soft reset
SRX
Channel 0: LPDDR4,50MHz
CS = 0
MR0=0x18
MR4=0x1
MR5=0x1
MR8=0x8
MR12=0x4D
MR14=0x4D
MR18=0x0
MR19=0x0
MR24=0x8
MR25=0x0
CS = 1
MR0=0x18
MR4=0x1
MR5=0x1
MR8=0x8
MR12=0x4D
MR14=0x4D
MR18=0x0
MR19=0x0
MR24=0x8
MR25=0x0
Bus Width=32 Col=10 Bank=8 Row=15/15 CS=2 Die Bus-Width=16 Size=2048MB
Channel 1: LPDDR4,50MHz
CS = 0
MR0=0x18
MR4=0x1
MR5=0x1
MR8=0x8
MR12=0x4D
MR14=0x4D
MR18=0x0
MR19=0x0
MR24=0x8
MR25=0x0
CS = 1
MR0=0x18
MR4=0x1
MR5=0x1
MR8=0x8
MR12=0x4D
MR14=0x4D
MR18=0x0
MR19=0x0
MR24=0x8
MR25=0x0
Bus Width=32 Col=10 Bank=8 Row=15/15 CS=2 Die Bus-Width=16 Size=2048MB
256B stride
channel 0
CS = 0
MR0=0x18
MR4=0x1
MR5=0x1
MR8=0x8
MR12=0x72
MR14=0x72
MR18=0x0
MR19=0x0
MR24=0x8
MR25=0x0
CS = 1
MR0=0x18
MR4=0x1
MR5=0x1
MR8=0x8
MR12=0x72
MR14=0x72
MR18=0x0
MR19=0x0
MR24=0x8
MR25=0x0
channel 1
CS = 0
MR0=0x18
MR4=0x1
MR5=0x1
MR8=0x8
MR12=0x72
MR14=0x72
MR18=0x0
MR19=0x0
MR24=0x8
MR25=0x0
CS = 1
MR0=0x18
MR4=0x1
MR5=0x1
MR8=0x8
MR12=0x72
MR14=0x72
MR18=0x0
MR19=0x0
MR24=0x8
MR25=0x0
channel 0 training pass!
channel 1 training pass!
change freq to 400MHz 0,1
channel 0
CS = 0
MR0=0x18
MR4=0x1
MR5=0x1
MR8=0x8
MR12=0x72
MR14=0x72
MR18=0x0
MR19=0x0
MR24=0x8
MR25=0x0
CS = 1
MR0=0x18
MR4=0x1
MR5=0x1
MR8=0x8
MR12=0x72
MR14=0x72
MR18=0x0
MR19=0x0
MR24=0x8
MR25=0x0
channel 1
CS = 0
MR0=0x18
MR4=0x1
MR5=0x1
MR8=0x8
MR12=0x72
MR14=0x72
MR18=0x0
MR19=0x0
MR24=0x8
MR25=0x0
CS = 1
MR0=0x18
MR4=0x1
MR5=0x1
MR8=0x8
MR12=0x72
MR14=0x72
MR18=0x0
MR19=0x0
MR24=0x8
MR25=0x0
channel 0 training pass!
channel 1 training pass!
change freq to 800MHz 1,0
ch 0 ddrconfig = 0x101, ddrsize = 0x2020
ch 1 ddrconfig = 0x101, ddrsize = 0x2020
pmugrf_os_reg[2] = 0x3AA1FAA1, stride = 0xD
OUT
Boot1: 2018-08-06, version: 1.15
CPUId = 0x0
ChipType = 0x10, 276
SdmmcInit=2 0
BootCapSize=100000
UserCapSize=29820MB
FwPartOffset=2000 , 100000
mmc0:cmd8,20
mmc0:cmd5,20
mmc0:cmd55,20
mmc0:cmd1,20
mmc0:cmd8,20
mmc0:cmd5,20
mmc0:cmd55,20
mmc0:cmd1,20
mmc0:cmd8,20
mmc0:cmd5,20
mmc0:cmd55,20
mmc0:cmd1,20
SdmmcInit=0 1
StorageInit ok = 68221
SecureMode = 0
SecureInit read PBA: 0x4
SecureInit read PBA: 0x404
SecureInit read PBA: 0x804
SecureInit read PBA: 0xc04
SecureInit read PBA: 0x1004
SecureInit read PBA: 0x1404
SecureInit read PBA: 0x1804
SecureInit read PBA: 0x1c04
SecureInit ret = 0, SecureMode = 0
GPT 0x3190d20 signature is wrong
LoadTrust Addr:0x4000
No find bl30.bin
Load uboot, ReadLba = 2000
Load OK, addr=0x200000, size=0xe4394
RunBL31 0x10000
NOTICE: BL31: v1.3(debug):d80d566
NOTICE: BL31: Built : 09:42:16, Nov 21 2018
NOTICE: BL31: Rockchip release version: v1.1
INFO: GICv3 with legacy support detected. ARM GICV3 driver initialized in EL3
INFO: Using opteed sec cpu_context!
INFO: boot cpu mask: 0
INFO: plat_rockchip_pmu_init(1162): pd status 3e
INFO: BL31: Initializing runtime services
INFO: BL31: Initializing BL32
INF [0x0] TEE-CORE:init_primary_helper:337: Initializing (1.1.0-195-g8f090d20 #6 Fri Dec 7 06:11:20 UTC 2018 aarch64)
INF [0x0] TEE-CORE:init_primary_helper:338: Release version: 1.2
INF [0x0] TEE-CORE:init_teecore:83: teecore inits done
INFO: BL31: Preparing for EL3 exit to normal world
INFO: Entry point address = 0x200000
INFO: SPSR = 0x3c9
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