|
发表于 2018-3-4 14:28:37
只看该作者
沙发
自己尝试改了下 dts,还是没有 ttyS1
diff --git a/arch/arm64/boot/dts/rk3328-roc-cc-port.dtsi b/arch/arm64/boot/dts/rk3328-roc-cc-port.dtsi
index a66214d..10c4af1 100644
--- a/arch/arm64/boot/dts/rk3328-roc-cc-port.dtsi
+++ b/arch/arm64/boot/dts/rk3328-roc-cc-port.dtsi
@@ -53,6 +53,60 @@
status = "okay";
};
+ aliases {
+ serial0 = &uart0;
+ serial1 = &uart1;
+ serial2 = &uart_dbg;
+ };
+
+ uart0: serial@ff110000 {
+ compatible = "rockchip,serial";
+ reg = <0x0 0xff110000 0x0 0x100>;
+ interrupts = <GIC_SPI 55 IRQ_TYPE_LEVEL_HIGH>;
+ clock-frequency = <24000000>;
+ clocks = <&clk_uart0>, <&clk_gates16 11>;
+ clock-names = "sclk_uart", "pclk_uart";
+ reg-shift = <2>;
+ reg-io-width = <4>;
+ dmas = <&pdma 2>, <&pdma 3>;
+ #dma-cells = <2>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&uart0_xfer &uart0_cts &uart0_rts>;
+ status = "disabled";
+ };
+
+ uart1: serial@ff120000 {
+ compatible = "rockchip,serial";
+ reg = <0x0 0xff120000 0x0 0x100>;
+ interrupts = <GIC_SPI 56 IRQ_TYPE_LEVEL_HIGH>;
+ clock-frequency = <24000000>;
+ clocks = <&clk_uart1>, <&clk_gates16 12>;
+ clock-names = "sclk_uart", "pclk_uart";
+ reg-shift = <2>;
+ reg-io-width = <4>;
+ dmas = <&pdma 4>, <&pdma 5>;
+ #dma-cells = <2>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&uart1_xfer &uart1_cts &uart1_rts>;
+ status = "okey";
+ };
+
+ uart_dbg: serial@ff130000 {
+ compatible = "rockchip,serial";
+ reg = <0x0 0xff130000 0x0 0x100>;
+ interrupts = <GIC_SPI 57 IRQ_TYPE_LEVEL_HIGH>;
+ clock-frequency = <24000000>;
+ clocks = <&clk_uart2>, <&clk_gates16 13>;
+ clock-names = "sclk_uart", "pclk_uart";
+ reg-shift = <2>;
+ reg-io-width = <4>;
+ dmas = <&pdma 6>, <&pdma 7>;
+ #dma-cells = <2>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&uart2m1_xfer>;
+ status = "disabled";
+ };
+
io-domains {
status = "okay";
@@ -378,11 +432,20 @@
};
&uart0 {
- status = "disabled";
- dma-names = "!tx", "!rx";
- pinctrl-0 = <&uart0_xfer &uart0_cts>;
+ status = "disabled";
+ dma-names = "!tx", "!rx";
+ pinctrl-0 = <&uart0_xfer &uart0_cts>;
+};
+
+&uart1{
+ status = "okey";
};
+&uart_dbg{
+ status = "okey";
+};
+ |
|