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fireflay开发板DDR怎么只跑到200MHz，CPU支持到533的能否达到？
发表于 2014-12-1 09:17:50
浏览：11277
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如题，接上串口后发现DDR3只跑到200MHz，CPU支持到533的能否达到？
在rk3288 datasheet中标明支持的533MHz
在开发板启动log中看到的DDR DEBUG信息，只有200MHz
[ 0.588418] DDR DEBUG: version 1.00 20140603
[ 0.588451] DDR DEBUG: Channel a:
[ 0.588461] DDR DEBUG: DDR3 Device
[ 0.588476] DDR DEBUG: Bus Width=32 Col=10 Bank=8 Row=15 CS=1 Total Capability=1024MB
[ 0.588489] DDR DEBUG: Channel b:
[ 0.588497] DDR DEBUG: DDR3 Device
[ 0.588511] DDR DEBUG: Bus Width=32 Col=10 Bank=8 Row=15 CS=1 Total Capability=1024MB
[ 0.588524] DDR DEBUG: addr=0xd60000
[ 0.588535] DDR DEBUG: stride=9, size=256, halfcap=40000000
[ 0.588546] DDR DEBUG: socAddr[0]=0xd60000, socAddr[1]=0xd60100
[ 0.588557] DDR DEBUG: chAddr[0]=0xd60000, chAddr[1]=0xd60000
[ 0.588571] DDR DEBUG: dtar[0]=0x1ac000, dtar[1]=0x1ac000
[ 0.588624] DDR DEBUG: init success!!! freq=200MHz
[ 0.588634] DDR DEBUG: Channel a:
[ 0.588648] DDR DEBUG: DTONE=0x1, DTERR=0x0, DTIERR=0x0, DTPASS=4,0, DGSL=1,1 extra clock, DGPS=180,90
[ 0.588664] DDR DEBUG: DTONE=0x1, DTERR=0x0, DTIERR=0x0, DTPASS=4,0, DGSL=1,1 extra clock, DGPS=180,90
[ 0.588681] DDR DEBUG: DTONE=0x1, DTERR=0x0, DTIERR=0x0, DTPASS=4,0, DGSL=1,1 extra clock, DGPS=180,90
[ 0.588697] DDR DEBUG: DTONE=0x1, DTERR=0x0, DTIERR=0x0, DTPASS=4,0, DGSL=1,1 extra clock, DGPS=180,90
[ 0.588713] DDR DEBUG: ZERR=0, ZDONE=0, ZPD=0x0, ZPU=0x0, OPD=0x0, OPU=0x0
[ 0.588725] DDR DEBUG: DRV Pull-Up=0x19, DRV Pull-Dwn=0x19
[ 0.588736] DDR DEBUG: ODT Pull-Up=0x2, ODT Pull-Dwn=0x2
[ 0.588746] DDR DEBUG: Channel b:
[ 0.588759] DDR DEBUG: DTONE=0x1, DTERR=0x0, DTIERR=0x0, DTPASS=4,0, DGSL=1,1 extra clock, DGPS=180,90
[ 0.588775] DDR DEBUG: DTONE=0x1, DTERR=0x0, DTIERR=0x0, DTPASS=4,0, DGSL=1,1 extra clock, DGPS=180,90
[ 0.588791] DDR DEBUG: DTONE=0x1, DTERR=0x0, DTIERR=0x0, DTPASS=4,0, DGSL=1,1 extra clock, DGPS=180,90
[ 0.588807] DDR DEBUG: DTONE=0x1, DTERR=0x0, DTIERR=0x0, DTPASS=4,0, DGSL=1,1 extra clock, DGPS=180,90
[ 0.588822] DDR DEBUG: ZERR=0, ZDONE=0, ZPD=0x0, ZPU=0x0, OPD=0x0, OPU=0x0
[ 0.588834] DDR DEBUG: DRV Pull-Up=0x19, DRV Pull-Dwn=0x19
[ 0.588845] DDR DEBUG: ODT Pull-Up=0x2, ODT Pull-Dwn=0x2
[ 0.609649] bio: create slab <bio-0> at 0
[ 0.610304] Enter firefly_noatx8_init
[ 0.610457] firefly_noatx8_probe 51
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