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【Linux】
关于RK3399内核烧写问题
发表于 2020-9-17 17:14:02
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RK3399Pro核心板通过AndroidTool工具烧写kernel.img过后，系统上电一直重启，报如找不到设备树错误，kernel.img是官方提供的SDK编译出来的。
U-Boot 2017.09-03654-gc07ae7246e (May 25 2020 - 16:33:57 +0800)
Model: Rockchip RK3399 Evaluation Board
PreSerial: 2
DRAM: 3.8 GiB
Sysmem: init
Relocation Offset is: f5bd1000
Using default environment
dwmmc@fe320000: 1, sdhci@fe330000: 0
Card did not respond to voltage select!
mmc_init: -95, time 9
switch to partitions #0, OK
mmc0(part 0) is current device
Bootdev: mmc 0
MMC0: HS400, 150Mhz
PartType: EFI
boot mode: normal
Read kernel dtb failed, ret=-19
Model: Rockchip RK3399 Evaluation Board
rockchip_set_serialno: could not find efuse device
CLK: (uboot. arml: enter 816000 KHz, init 816000 KHz, kernel 0N/A)
CLK: (uboot. armb: enter 24000 KHz, init 24000 KHz, kernel 0N/A)
aplll 816000 KHz
apllb 24000 KHz
dpll 800000 KHz
cpll 24000 KHz
gpll 800000 KHz
npll 600000 KHz
vpll 24000 KHz
aclk_perihp 133333 KHz
hclk_perihp 66666 KHz
pclk_perihp 33333 KHz
aclk_perilp0 266666 KHz
hclk_perilp0 88888 KHz
pclk_perilp0 44444 KHz
hclk_perilp1 100000 KHz
pclk_perilp1 50000 KHz
Net: No ethernet found.
Hit key to stop autoboot('CTRL+C'): 0
ANDROID: reboot reason: "(none)"
Not AVB images, AVB skip
Fdt Ramdisk skip relocation
Booting IMAGE kernel at 0x00280000 with fdt at 0x8300000...
## Booting Android Image at 0x0027f800 ...
Kernel load addr 0x00280000 size 22107 KiB
## Flattened Device Tree blob at 08300000
Booting using the fdt blob at 0x8300000
XIP Kernel Image ... OK
reserving fdt memory region: addr=8300000 size=1b000
'reserved-memory' region@110000: addr=110000 size=f0000
Using Device Tree in place at 0000000008300000, end 000000000831dfff
Adding bank: 0x00200000 - 0x08400000 (size: 0x08200000)
Adding bank: 0x0a200000 - 0xf8000000 (size: 0xede00000)
Total: 482.673 ms
Starting kernel ...
"Synchronous Abort" handler, esr 0x96000035
* Relocate offset = 00000000f5bd1000
* ELR(PC) = ffffffff0bad20e4
* LR = ffffffff0b7fa50c
* SP = 00000000f3dc3e60
* ESR_EL2 = 0000000096000035
EC[31:26] == 100101, Exception from a Data abort, from current exception level
IL[25] == 1, 32-bit instruction trapped
* DAIF = 00000000000003c0
D[9] == 1, DBG masked
A[8] == 1, ABORT masked
I[7] == 1, IRQ masked
F[6] == 1, FIQ masked
* SPSR_EL2 = 00000000800003c9
D[9] == 1, DBG masked
A[8] == 1, ABORT masked
I[7] == 1, IRQ masked
F[6] == 1, FIQ masked
M[4] == 0, Exception taken from AArch64
M[3:0] == 1001, EL2h
* SCTLR_EL2 = 0000000030c50830
I[12] == 0, Icache disabled
C[2] == 0, Dcache disabled
M[0] == 0, MMU disabled
* HCR_EL2 = 000000000800003a
* VBAR_EL2 = 00000000f5dd1800
* TTBR0_EL2 = 00000000f7ff0000
x0 : 0000000008300178 x1 : 0000000008300088
x2 : ffffffffffffffff x3 : 0000000000000000
x4 : 0000000000280000 x5 : 0000000000000001
x6 : 0000000000000008 x7 : 0000000000000000
x8 : 00000000f3dc3f40 x9 : 0000010000000000
x10: 000000000a200023 x11: 0000000000000002
x12: 0000000000000002 x13: 00000000f3dc3f6c
x14: 0000000008300000 x15: 00000000f5dd25a8
x16: 0000000000000000 x17: 0000000000000000
x18: 00000000f3dc8d10 x19: 0000000008300000
x20: 0000000000000000 x21: 00000000025f7000
x22: 00000000027d8458 x23: 00000000f3dc4298
x24: 0000000000000000 x25: 0000000000280000
x26: 00000000f5dd2fdc x27: 0000000000000400
x28: 0000000000280000 x29: 00000000f3dc4040
SP:
f3dc3e60: 00000000 00000000 00000000 00000000
f3dc3e70: 00000000 00000000 f5e981da 00000000
f3dc3e80: 00000000 00000000 00000000 00000000
f3dc3e90: f5e98221 00000000 f5e98247 00000000
f3dc3ea0: f5e98294 00000000 f5e982e1 00000000
f3dc3eb0: f5e98321 00000000 f5e98361 00000000
f3dc3ec0: f5e9839e 00000000 00000000 00000000
f3dc3ed0: 00000000 00000000 f5e983db 00000000
f3dc3ee0: f3dc4040 00000000 f5dd1a0c 00000000
f3dc3ef0: 08300000 00000000 f5e4bbfc 00000000
f3dc3f00: f7ff0000 00000000 0800003a 00000000
f3dc3f10: 30c50830 00000000 f3dc3e60 00000000
f3dc3f20: 800003c9 00000000 f5dd1800 00000000
f3dc3f30: 000003c0 00000000 96000035 00000000
f3dc3f40: 016a30e4 00000000 08300178 00000000
f3dc3f50: 08300088 00000000 ffffffff ffffffff
Call trace:
PC: [< ffffffff0bad20e4 >]
LR: [< ffffffff0b7fa50c >]
Stack:
[< ffffffff0bad20e4 >]
[< ffffffff0b7fa50c >]
[< ffffffff0b92f004 >]
[< 002176f4 >]
[< 00217188 >]
[< 00206708 >]
[< 00224f24 >]
[< 00225a44 >]
[< 00206fec >]
[< 0022a8d8 >]
[< 002156e0 >]
[< 00215880 >]
[< 00214fcc >]
[< 0021549c >]
[< 00215880 >]
[< 00214f84 >]
[< 00229ddc >]
[< 00213970 >]
[< 002164bc >]
[< 0027bffc >]
[< 00216648 >]
[< 00201b2c >]
Copy above stack info to a file(eg. dump.txt), and
execute command in your U-Boot project: ./scripts/stacktrace.sh dump.txt
Resetting CPU ...
WARN: PSCI sysreset is disabled
DDR Version 1.20 20190314
In
soft reset
SRX
Channel 0: LPDDR3, 800MHz
CS = 0
MR0=0x58
MR1=0x58
MR2=0x58
MR3=0x58
MR4=0x3
MR5=0x1
MR6=0x5
MR7=0x0
MR8=0x1F
MR9=0x1F
MR10=0x1F
MR11=0x1F
MR12=0x1F
MR13=0x1F
MR14=0x1F
MR15=0x1F
MR16=0x1F
CS = 1
MR0=0x58
MR1=0x58
MR2=0x58
MR3=0x58
MR4=0x3
MR5=0x1
MR6=0x5
MR7=0x0
MR8=0x1F
MR9=0x1F
MR10=0x1F
MR11=0x1F
MR12=0x1F
MR13=0x1F
MR14=0x1F
MR15=0x1F
MR16=0x1F
Bus Width=32 Col=10 Bank=8 Row=15/15 CS=2 Die Bus-Width=32 Size=2048MB
Channel 1: LPDDR3, 800MHz
CS = 0
MR0=0x58
MR1=0x58
MR2=0x58
MR3=0x58
MR4=0x3
MR5=0x1
MR6=0x5
MR7=0x0
MR8=0x1F
MR9=0x1F
MR10=0x1F
MR11=0x1F
MR12=0x1F
MR13=0x1F
MR14=0x1F
MR15=0x1F
MR16=0x1F
CS = 1
MR0=0x58
MR1=0x58
MR2=0x58
MR3=0x58
MR4=0x3
MR5=0x1
MR6=0x5
MR7=0x0
MR8=0x1F
MR9=0x1F
MR10=0x1F
MR11=0x1F
MR12=0x1F
MR13=0x1F
MR14=0x1F
MR15=0x1F
MR16=0x1F
Bus Width=32 Col=10 Bank=8 Row=15/15 CS=2 Die Bus-Width=32 Size=2048MB
256B stride
ch 0 ddrconfig = 0x101, ddrsize = 0x2020
ch 1 ddrconfig = 0x101, ddrsize = 0x2020
pmugrf_os_reg[2] = 0x3AA0DAA0, stride = 0xD
OUT
Boot1: 2018-08-06, version: 1.15
CPUId = 0x0
ChipType = 0x10, 275
SdmmcInit=2 0
BootCapSize=100000
UserCapSize=14910MB
FwPartOffset=2000 , 100000
mmc0:cmd8,20
mmc0:cmd5,20
mmc0:cmd55,20
mmc0:cmd1,20
mmc0:cmd8,20
mmc0:cmd5,20
mmc0:cmd55,20
mmc0:cmd1,20
mmc0:cmd8,20
mmc0:cmd5,20
mmc0:cmd55,20
mmc0:cmd1,20
SdmmcInit=0 1
StorageInit ok = 68307
SecureMode = 0
SecureInit read PBA: 0x4
SecureInit read PBA: 0x404
SecureInit read PBA: 0x804
SecureInit read PBA: 0xc04
SecureInit read PBA: 0x1004
SecureInit read PBA: 0x1404
SecureInit read PBA: 0x1804
SecureInit read PBA: 0x1c04
SecureInit ret = 0, SecureMode = 0
GPT part: 0, name: uboot, start:0x4000, size:0x2000
GPT part: 1, name: trust, start:0x6000, size:0x2000
GPT part: 2, name: misc, start:0x8000, size:0x2000
GPT part: 3, name: boot, start:0xa000, size:0x10000
GPT part: 4, name: recovery, start:0x1a000, size:0x10000
GPT part: 5, name: backup, start:0x2a000, size:0x10000
GPT part: 6, name: rootfs, start:0x5a000, size:0x1cc4fdf
find partition:uboot OK. first_lba:0x4000.
find partition:trust OK. first_lba:0x6000.
LoadTrust Addr:0x6000
No find bl30.bin
Load uboot, ReadLba = 4000
Load OK, addr=0x200000, size=0xf3834
RunBL31 0x10000
NOTICE: BL31: v1.3(debug):cd61876
NOTICE: BL31: Built : 16:25:54, Jan 23 2019
NOTICE: BL31: Rockchip release version: v1.1
INFO: GICv3 with legacy support detected. ARM GICV3 driver initialized in EL3
INFO: Using opteed sec cpu_context!
INFO: boot cpu mask: 0
INFO: plat_rockchip_pmu_init(1181): pd status 3e
INFO: BL31: Initializing runtime services
INFO: BL31: Initializing BL32
INF [0x0] TEE-CORE:init_primary_helper:337: Initializing (1.1.0-195-g8f090d20 #6 Fri Dec 7 06:11:20 UTC 2018 aarch64)
INF [0x0] TEE-CORE:init_primary_helper:338: Release version: 1.2
INF [0x0] TEE-CORE:init_teecore:83: teecore inits done
INFO: BL31: Preparing for EL3 exit to normal world
INFO: Entry point address = 0x200000
INFO: SPSR = 0x3c9
U-Boot 2017.09-03654-gc07ae7246e (May 25 2020 - 16:33:57 +0800)
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